PD Clocking Engineer

About the role

Responsible for developing, validating, and maintaining implementation flows, clock-tree methodologies, timing correlation, QoR convergence strategies, and automation frameworks used across multiple projects.

What you'll do

• Own end-to-end clocking methodology including CTS architecture, clock latency/skew management, clock QoR reviews, and timing convergence strategies
• Develop, certify, and maintain PnR implementation flows across technology nodes and design styles
• Drive flow correlation between Tile PnR, Full-Chip Timing (FCT), STA, and signoff environments to ensure predictable closure
• Define implementation recipes, optimisation strategies, and best practices for timing, congestion, power, and area closure
• Develop automation using Tcl/Python/Shell to improve productivity, debug efficiency, and flow robustness

What you need

• 1–3 years in electrical & electronics
• VLSI
• Python
• B.Tech or B.E.