PD PNR Engineer

About the role

MTS Silicon Design Engineer – Tile PnR Role Summary Responsible for end-to-end physical implementation and convergence of complex SoC/IP tiles. The engineer will drive floorplanning, place-and-route, timing closure, power and area optimization, physical verification readiness, and ECO implementation while collaborating closely with RTL, architecture, CAD, timing, clocking, and full-chip teams.

What you'll do

• Own end-to-end implementation and convergence of assigned tiles from netlist handoff to signoff
• Drive floorplanning, placement, CTS, routing, timing, power, congestion, and area optimization
• Perform timing analysis and implement setup/hold/ECO fixes to achieve QoR targets
• Debug implementation issues related to timing, congestion, DRC, EMIR, CDC, and physical integration
• Collaborate with RTL, Architecture, Clocking, DFT, Integration, and CAD teams to resolve design challenges

What you need

• 7–10 years in electrical & electronics
• VLSI
• Python
• Perl
• B.Tech or B.E.

Good to have

• Machine learning