PD Timing lead

About the role

MTS Silicon Design Engineer – Constraints & Full-Chip Timing (FCT) Role Summary Responsible for developing, validating, and maintaining timing constraints and driving full-chip timing convergence for complex SoCs. The engineer will own SDC methodology, timing signoff quality, cross-domain timing closure, and collaborate with RTL, Architecture, Tile PnR, Clocking, DFT, and Full-Chip teams to achieve timing signoff targets across all project milestones.

What you'll do

• Develop, validate, and maintain block, subsystem, and SoC-level timing constraints (SDC)
• Perform comprehensive timing analysis and closure for full-chip and partition-level designs
• Analyze setup, hold, SI, OCV, AOCV, POCV, CDC-related, and mode-specific timing violations
• Drive timing convergence across multiple corners, modes, and milestone releases
• Own timing signoff readiness and ensure timing quality across all project deliverables

What you need

• 7–10 years in electrical & electronics
• VLSI
• Python
• Shell scripting
• Perl
• B.Tech or B.E. or M.Tech

Good to have

• Machine learning