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Principal Design Engineer

Cadence·Pune

Pay not stated8–10 yrsFull-time

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About the role

As a member of the Functional Safety Design Verification Team for Xtensa processors you will be responsible for development and verification of hardware and software safety mechanisms. You will implement simulation or emulation test benches, assembly/C language diagnostics, assertion checkers or coverage monitors to meet target safety and product verification goals.

What you'll do

  • Be responsible for development and verification of hardware and software safety mechanisms
  • Implement simulation or emulation test benches, assembly/C language diagnostics
  • Also assist with fault simulation and analyzing coverage information
  • Work closely with the RTL, EDA, and Functional Safety teams

What you need

  • 8–10 years in electrical & electronics
  • C
  • Verilog
  • Perl
  • Linux
  • B.Tech or B.E.

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