Principal Design Engineer

About the role

We are looking for modeling engineers to help develop performance models, perform architectural tradeoff analysis, and enable data driven design decisions for our next generation DDR memory controller architectures that can meet today’s complex SoC and workload requirements. Hardware modelling experience (C++/SystemC/TLM/Python) and computer architecture foundation is desired.

What you'll do

• Develop cycle-level performance models in SystemC or C++
• Correlate performance models to match RTL configurations and traffic conditions
• Work with Memory Architects to understand feature requirements, architectural specifications and implement in the model
• Analyze architectural trade-offs (throughput, hardware cost) across different scenarios and architectural choices
• Develop synthetic memory traffic/traces that are representative of real-world applications (CPU, GPU, DSP, NoC, etc)

What you need

• 8–14 years in electrical & electronics
• C++
• B.Tech or B.E. or M.Tech

Good to have

• Python
• UVM
• Verilog
• Pandas