Principal Engineer, Design verification

About the role

You will think through design corner cases and be able to write relevant cover points. Collaborate with digital design team to debug test cases and deliver functionally accurate designs. Close coverage measures to identify verification holes and to show progress towards tape-out. Technical support to internal and external model users

What you'll do

• Test bench Development in System Verilog targeting complete functionality coverage
• Support of System Verilog assertion and coverage-driven methodology
• Support of design verification methodology improvements
• Run directed and constrained-random verification tests
• Think through design corner cases and be able to write relevant cover points

What you need

• 10–18 years in electrical & electronics
• Verilog
• Test cases
• Machine learning
• LLMs
• Any graduate

What you get