Principal Engineer-Verification

About the role

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization?

What you'll do

• Responsible for verifying digital integrated circuits at the block or device level
• Own the verification of complex digital integrated circuits at the block, subsystem, or device level
• Plan verification activities, develop testbenches, and execute tests
• Develop verification platforms using the UVM methodology and SystemVerilog
• Deliver verified designs at the Device, Subsystem or Block level

What you need

• 10–18 years in electrical & electronics
• UVM
• Verilog
• Any graduate