Principal Software Engineer

About the role

Design and implement a full, dedicated, and flexible (e.g., UVM based) verification environment Involved with all aspects of pre-silicon verification at unit and system level to ensure functional correctness and performance of the overall system-level solution. Defining verification strategy from IP to top digital integration

What you'll do

• Design and implement a full, dedicated, and flexible (e.g., UVM based) verification environment
• Defining verification strategy from IP to top digital integration
• Define requirements for block level and full-chip level verification infrastructure
• Create test plans for unit-level and chip-level verification and post-silicon validation
• Create coverage monitors and drive coverage to required quality targets

What you need

• 5–10 years in software engineering
• C++
• Shell scripting
• UVM
• Test cases
• C
• Verilog
• M.Sc or B.Tech or B.E.

Good to have

• Python
• Perl