R&D Engineering, Sr Manager

About the role

R&D Engineering, Sr Manager at Synopsys (incl. Ansys). Bridge the gap between Emulation IP capabilities and Design IP verification needs across both Controller and PHY domains for high speed interfaces like PCIe and DDR.

What you'll do

• Bridge the gap between Emulation IP capabilities and Design IP verification needs across both Controller and PHY domains for high speed interfaces like PCIe and DDR
• Define technical requirements for Emulation IP, working directly with IP development and verification teams to ensure correct implementation and deployment on Zebu…
• Track and report key metrics on Emulation IP quality, performance, and coverage, driving continuous improvement across verification workflows
• Stay ahead of evolving PCIe and DDR standards, interpret specification updates, ECNs, and errata
• Review and validate test plans for Emulation IP and Design IP, ensuring completeness, traceability, and alignment with product quality goals

What you need

• 15–27 years in electrical & electronics
• Test cases
• Any graduate