R&D Engineering, Sr Manager

About the role

R&D Engineering, Sr Manager at Synopsys (incl. Ansys). Lead a cross-functional team through the complete embedded memory development cycle, from bit cell analysis and architecture definition through circuit design, layout.

What you'll do

• Lead a cross-functional team through the complete embedded memory development cycle, from bit cell analysis and architecture definition through circuit design, layout
• Drive SRAM, register file, TCAM, and ROM compiler development, balancing performance, power, area, and yield across advanced FinFET technology nodes
• Own schematic entry, transistor-level simulation, layout planning, and interface with CAD teams for full physical verification and timing model delivery
• Design and implement low-power, area-efficient memory circuits and architectures optimized for deep submicron and FinFET process variations
• Coordinate daily activities across your engineering team, prioritize workloads across multiple concurrent projects

What you need

• 10–18 years in electrical & electronics
• Circuit design
• Python
• Perl
• Physics
• B.Tech or B.E. or M.Tech or M.Sc