Senior Design Lead

About the role

We are seeking a SoC Design Verification Lead with 8-15 years of experience in ASIC/SoC verification to lead end-to-end verification activities for complex SoC programs. The candidate will be responsible for verification strategy, testbench architecture, verification closure, and mentoring the verification team through tape-out.

What you'll do

• Lead SoC verification activities from specification review to tape-out
• Define verification plans, methodologies, and full-chip verification strategies
• Architect and develop reusable SystemVerilog/UVM based verification environments
• Drive constrained-random verification, regression execution, coverage closure, and sign-off
• Develop and review functional coverage models and SystemVerilog Assertions (SVA)

What you need

• 8–15 years in ui/ux & product design
• Verilog
• C
• UVM
• C++
• Test cases
• Any graduate

Good to have

• Prototyping
• FPGA
• Shell scripting
• Python
• Perl

What you get