Senior Design Lead

About the role

We are seeking a Senior Design Verification Engineer with 8 to 15 years of experience in ASIC/SoC verification and deep expertise in one or more next-generation technologies such as PCIe Gen5/Gen6, LPDDR5/LPDDR6, HBM3/HBM4, UCIe, Ethernet, ARM Neoverse, CHI , and advanced SoC interconnects.

What you'll do

• Develop and maintain reusable SystemVerilog/UVM based verification environments
• Create verification plans, test cases, sequences, scoreboards, and checkers
• Develop constrained-random and directed tests to validate complex protocol and architectural features
• Implement functional coverage models and SystemVerilog Assertions (SVA)
• Execute regressions, analyze failures, and drive verification closure

What you need

• 8–15 years in ui/ux & product design
• Verilog
• UVM
• C++
• Machine learning
• C
• Python
• Any graduate

Good to have

• Prototyping
• FPGA
• Perl
• Test cases