Senior DFT Engineer

About the role

We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan chain insertion, compression scan technologies, memory built-in self-test (MBIST) and automatic test pattern generation (ATPG) is required for this position. It is highly desirable for candidate to possess hands-on knowledge of synthesis, verification and debugging Verilog testbenches.

What you need

• 5–15 years in electrical & electronics
• MIS reporting
• Any graduate

Good to have

• Verilog