Senior Implementation Engineer

About the role

We are seeking a highly experienced ASIC Physical Design Engineer with 12+ years of hands-on expertise in full-chip and hierarchical SoC physical design. This role requires deep technical expertise in advanced technology nodes, strong problem-solving capability, and leadership in driving chip closure from netlist to GDSII.

What you'll do

• Lead chip-level hierarchical floor planning and block-level integration
• Drive partitioning strategy , partition push-down, and hierarchical design implementation
• Own pin planning, IO planning, bump planning, and bump routing for complex SoCs
• Define and execute power planning (ring/mesh/grid architecture, multi-domain handling)
• Perform and manage full-chip CTS and clock architecture optimization

What you need

• 12–22 years in software engineering
• Python
• Last-mile delivery
• VLSI
• B.Tech or B.E. or M.Tech