Senior Technical Architect

About the role

We are seeking a highly technical and execution-driven Physical Design Chip Lead to spearhead the structural design, implementation, and physical sign-off of our next-generation, high-performance SoCs. In this role, you will own the entire full-chip physical design lifecycle—from early architectural feasibility, floorplanning, and synthesis through final GDSII tape-out.

What you'll do

• Drive the execution of the entire hierarchical RTL-to-GDSII physical design flow, including synthesis, floorplanning, place & route (PnR), clock tree synthesis (CTS)
• Define the physical implementation strategy, schedule milestones, and allocate resources across block-level and full-chip integration tasks. Identify and mitigate…
• Partner with SoC architects to conduct early feasibility studies. Drive top-level floorplanning, package/bump placement, macro integration
• Establish strict sign-off criteria and methodologies for the project across all domains: Static Timing Analysis (STA), Electromigration and IR Drop (EMIR)
• Act as the primary engineering bridge between RTL Front-End, Design Verification (DV), DFT, Packaging, Signal/Power Integrity, and external Silicon Foundries

What you need

• 6–10 years in software engineering
• Python
• VLSI
• Power systems
• Structural design
• Any graduate