Senior Test Lead

About the role

Candidates with more than 8 years’ experience is mandatory. That includes planning verification and bring-up before tape-out, running the first days on the bench when silicon returns, and building repeatable coverage for high-speed interfaces and memory. Hire and develop the engineers who will perform these activities and be the technical point of contact when a board does not come up.

What you'll do

• Lead end-to-end functional validation on SoC / ASIC programs: test strategy, pre-silicon execution on emulation or FPGA, first-silicon bring-up
• Define bring-up checklists and coverage plans that design, firmware, and the lab can execute against
• Debug across board, package, silicon, and firmware with standard lab tools (JTAG/DAP, protocol analyzers, memory exercisers, scopes)
• Build and reuse test content for interfaces and memory (for example PCIe, DDR/LPDDR/HBM, Ethernet, USB) rather than starting from zero on every program
• Lead a mixed onsite and offshore team

What you need

• 8–14 years in quality assurance & testing
• UVM
• FPGA
• Any graduate