Solution Director

About the role

Candidates with minimum 20-25 years experience is mandatory Has participated in multiple ASIC/SoC verification till tapeout stage 1.Experience in ASIC/SoC Testbench definition 2.Experience to Build and maintain reusable block-level and sub-system testbenches using SystemVerilog and the Universal Verification Methodology (UVM)."

What you'll do

• Own and execute verification closure
• Own and lead End-End projects
• Experience to lead the micro-architecture and full-chip verification of our next-generation semiconductor products
• End-to-end ownership of complex IPs and subsystems, from defining functional specifications to managing final tape-out sign-off
• Architect robust, scalable UVM environments, solve critical architectural bottlenecks, and mentor a team of engineers to ensure first-pass silicon success

What you need

• 20–25 years in software engineering
• Python
• UVM
• Test cases
• Verilog
• VLSI
• Perl
• B.Tech or B.E.

Good to have

• Shell scripting
• C