- Can I apply
- Needs PhD · 8–14 yrs
- Pay
- Pay not stated
- Source
- From the company's careers page · today
- How to apply
- On Cisco's site (Workday): account needed, ~10–15 min
Early: posted 1 h ago on their own site
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About the role
Sr Mask Design Engineer at Renesas Electronics. Layout high performance Analog and Mixed Signal circuits using the latest Cadence Design Suite.
What you'll do
- Layout high performance Analog and Mixed Signal circuits using the latest Cadence Design Suite
- Perform IP level layout tasks including device placement, routing, matching techniques, shielding, guard rings, and parasitic-aware layout practices
- Work at multiple levels of hierarchy, from macro level (block level) to Top-level (ESD/Pad frame)
- Verify connectivity and design rules with Assura, Calibre, PVS
- Use QRC extraction to analyze and reduce noisy/sensitive coupling
What you need
- 2–5 years in electrical & electronics
- Accounts payable
- B.Tech or B.E.
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- Can I apply
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- Pay
- Pay not stated
- Source
- From the company's careers page · today
- How to apply
- On Cisco's site: account needed, ~10–15 min
Early: posted 1 h ago on their own site