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Sr Principal Design Engineer

Cadence·Noida

Pay not stated10–18 yrsFull-time

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About the role

B. Tech/M.Tech with 10+ years of relevant experience. Position is based in Bangalore/Noida, part of Cadence IP Group. Verification role for Serial and Interface Design IPs verification (PCIe, CCIX, CXL, USB, Ethernet, SATA/SAS, UFS, SPI, HDMI, MIPI, I3C) UVM testbench development to build a robust, scalable and efficient testbench to verify the design IPs.

What you'll do

  • Design Verification role for IP development team

What you need

  • 10–18 years in electrical & electronics
  • UVM
  • SAS
  • Test cases
  • System design
  • Customer success
  • Learning and development
  • B.Tech or B.E. or M.Tech

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