Sr Principal Design Engineer

About the role

The role requires the management of a Memory Controller DV group focusing on MDV verification including Constrained Random Functional Verification, Formal Property Verification, project DV status and execution, and mentorship of junior engineers.

What you'll do

• Additionally, this person will be responsible for ensuring that the design is in line with the technical and quality requirements set for the team
• Participate in Technical alignment with verification experts in defining verification strategy, architecting verification environment
• Represent DV and technically work/lead team interactions with RTL, Subsystem and Performance for design verification tasks
• Contribute towards defining, developing, and deploying new functional verification methodologies
• Participate in interactions with Marketing, AE and Release team when required

What you need

• 11–20 years in electrical & electronics
• UVM
• Verilog
• Test cases
• System design
• Customer success
• Learning and development
• B.Tech or B.E. or M.Tech or M.Sc