- Can I apply
- Open to any education · 8–14 yrs
- Pay
- Pay not stated
- Source
- From the company's careers page · today
- How to apply
- On Cisco's site (Workday): account needed, ~10–15 min
Early: posted 1 h ago on their own site
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About the role
As a Staff Design Verification Engineer at Analog Devices, you will provide technical leadership in developing verification strategies for our most complex analog and mixed-signal designs. You'll architect sophisticated verification environments, mentor junior engineers, and collaborate across organizational boundaries to ensure product quality and reliability.
What you need
- 7–10 years in electrical & electronics
- UVM
- Verilog
- Python
- Shell scripting
- Perl
- M.Sc or PhD
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