Staff Digital Verification Engineer

About the role

We are looking for a highly motivated Staff Digital Verification Engineer with 6-10 years of experience in ASIC/SoC verification. The ideal candidate will have strong expertise in System Verilog (SV) and UVM , along with hands-on experience in developing scalable verification environments, coverage-driven verification, and debugging complex RTL and gate-level issues.

What you'll do

• Expected to take ownership and lead verification efforts across IP, subsystem, and SoC-level projects and work independently
• Independently Architect and develop reusable verification environments using System Verilog and UVM
• Create constrained-random, directed, and scenario-based test cases
• Develop scoreboards, monitors, protocol checkers, assertions (SVA), and coverage models
• Analyze and debug RTL and gate-level simulation failures for timing and functional signoff

What you need

• 6–10 years in electrical & electronics
• UVM
• Verilog
• C++
• VLSI
• C
• Test cases
• B.Tech or B.E.

Good to have

• LLMs
• Git