- Can I apply
- Open to any education · 8–14 yrs
- Pay
- Pay not stated
- Source
- From the company's careers page · today
- How to apply
- On Cisco's site (Workday): account needed, ~10–15 min
Early: posted 1 h ago on their own site
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About the role
Be part of ASIC Design Verification team responsible for verification of IP/Block or Subsystem.
What you'll do
- Be part of a highly skilled ASIC Team working on latest technologies
- Responsible for overall IP/Block and Subsystem verification from Test plan creation, System Verilog/UVM testbench development to Sign-off
- Responsible for verification of IP/Block or Subsystem
What you need
- 6–10 years in electrical & electronics
- UVM
- Verilog
- Test cases
- VLSI
- Any graduate
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- Can I apply
- Open to any education · 8–14 yrs
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- Source
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- How to apply
- On Cisco's site (Workday): account needed, ~10–15 min
Early: posted 1 h ago on their own site
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- Can I apply
- Open to any education · 5–8 yrs
- Pay
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- Source
- From the company's careers page · today
- How to apply
- On Applied Materials' site (Workday): account needed, ~10–15 min
Early: posted 1 h ago on their own site
- Can I apply
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- Pay
- Pay not stated
- Source
- From the company's careers page · today
- How to apply
- On Cisco's site: account needed, ~10–15 min
Early: posted 1 h ago on their own site