Staff Physical Verification Engineer

About the role

Staff Physical Verification Engineer at PDC. We are seeking a Staff Physical Verification Engineer to own full-chip signoff for advanced SoC/ASIC designs.

What you'll do

• Lead methodologies and execution for DRC, LVS, PERC and related reliability checks, working closely with Place-n-route, analog/mixed-signal
• Own full-chip and block-level physical verification signoff, including DRC, LVS, ERC, PERC and antenna/ESD checks for multiple complex SoCs
• Drive tape-out readiness: manage PV schedules, track violations, converge to zero/signoff-acceptable errors, and deliver clean GDS
• Develop, maintain, and optimize PV flows and scripts (e.g., Calibre, ICV) for performance, robustness, and ease of use
• Define and enhance PERC and reliability rule checks (ESD, EOS, EM-related constraints, point-to-point resistance

What you need

• 8–12 years in electrical & electronics
• Inventory counting
• VLSI
• Python
• Perl
• Linux
• Travel booking
• B.Tech or B.E.

Good to have

• Root cause analysis