Staff Verification Engineer

About the role

We are seeking an experienced ASIC Verification Engineer to join our dynamic team. As a verification engineer, you will play a crucial role in ensuring the quality and reliability of our cutting-edge semiconductor designs. If you thrive in a collaborative environment and have a passion for solving complex challenges, this role is for you.

What you'll do

• Develop and execute comprehensive verification plans
• Close verification with coverage closure, ensuring high-quality results
• Apply standard ASIC verification techniques, including test planning, testbench creation, code and functional coverage, directed and random stimulus generation
• Create and enhance testbenches using SystemVerilog (OVM/UVM) or other standard testbench languages
• Implement reusable Verification IP (VIP) components

What you need

• 7–13 years in electrical & electronics
• UVM
• Verilog
• C++
• C
• Python
• Perl
• B.Tech or B.E.

Good to have

• VLSI