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Perform end‑to‑end physical design flow:FloorplanningPower planning (PG grid, IR)Placement & optimizationCTS (Clock Tree Synthesis)RoutingPost‑route optimizationAchieve timing closure across all modes and cornersResolve DRC, LVS, ERC and signoff violationsHandle low‑power design techniques:Multi‑Vt, Multi‑voltage (UPF)Power gating, clock gatingPerform physical verification and signoff:STA (Primetime)SI / CrosstalkIR drop & EM analysisWork on advanced nodes (7nm, 5nm, 3nm or below)Collaborate…
Jobgether·Remote
Jobgether·Remote
Jobgether·Remote
Hartford Global Services·India