ASIC Design and STA Engineer

About the role

Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work.

What you'll do

• Be in charge of full chip and/or chiplet level STA convergence from early stages to signoff
• Take part in top level floor plan and clock planning
• Optimize, together with CAD signoff flows and methodologies
• Digital Partitions' and analog IPs' timing integration, giving feedback to PD/RTL and driving convergence
• Work closely with logic design and DFT engineers to define and implement constraints for the various work modes, including their optimization for runtime and efficiency

What you need

• 3–6 yrs of experience
• VLSI
• B.Tech or B.E. or B.Sc or M.Sc