ASIC Design Engineer - Performance Monitoring

About the role

In this role, you should have real passion for RTL design implementation and methodologies that enable high quality system-level IP design.

What you'll do

• Be an integral part of the team defining and developing system-level RTL and methodologies to measure performance on the industry's leading GPUs/SOCs
• Design and implement RTL features - work through the entire design cycle for SOC
• Run and debug RTL checks to ensure design quality (e.g. CDC, RDC, Lint, Synthesis, Logic-Equivalence and more)
• Define, develop, and automate flows and methodologies to efficiently build and support a system-level IP
• Work with architects, designers, verification and SW engineers to accomplish your tasks

What you need

• 3–6 yrs of experience
• VLSI
• Verilog
• Python
• Perl
• B.Tech or B.E. or M.Tech