ASIC Design Verification Engineer | UVM | Exp 8+ Years

About the role

Define, design and verify ASIC and ASIC subsystems to be deployed in a range of Cisco platforms. Contribute to a multi-disciplined engineering team to meet the power, performance, and area goals for products. Design, document, and develop ASIC subsystems for release in high volume and quality. Help define the process, methods, and tools for design and implementation of complex developments.

What you'll do

• Architect block, cluster and top-level DV environment infrastructure
• Develop DV infrastructure from scratch
• Maintain and improve existing DV environments

What you need

• 8–14 yrs of experience
• VLSI
• UVM
• Any graduate