ASIC Design Verification Engineer | UVM | Exp. 8+ years

About the role

You will engage in dynamic collaboration with verification engineers, designers, and multi-functional teams, working together to ensure the successful verification of the ASIC throughout its lifecycle.

What you'll do

• Architect block, cluster and top-level DV environment infrastructure
• Develop DV infrastructure from scratch
• Maintain and improve existing DV environments
• Develop test plans and tests for qualifying design at block, cluster and higher-level environments with mix of constraint random and advised stimulus
• Ensure complete verification coverage through implementation and review of code and functional coverage

What you need

• 8–14 yrs of experience
• VLSI
• UVM
• Verilog
• Python
• Perl
• Test cases
• Any graduate

Good to have

• Routing and switching