ASIC Design Verification Engineer || Verilog, UVM, Testbench | Simulation || Exp 7+ years

About the role

Develop and implement verification plans and test benches using Simulation tools and methodologies. Collaborate with design and validation teams to identify verification requirements and coverage goals. Utilize emulation platforms to run large-scale verification tests and debug design issues. Analyse verification results, identify bugs, and work closely with design engineers to resolve issues.

What you'll do

• Develop and implement verification plans and test benches using Simulation tools and methodologies
• Collaborate with design and validation teams to identify verification requirements and coverage goals
• Analyse verification results, identify bugs, and work closely with design engineers to resolve issues

What you need

• 7–13 yrs of experience
• VLSI
• UVM
• Verilog
• Any graduate