ASIC DFT DV Engineer || System Verilog, UVM || JTAG, MBIST || Exp : 8+ years

About the role

Bangalore, India; Hyderabad, Telangāna, India The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world.

What you'll do

• Work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive high-quality DFT verification
• Responsible for thorough test planning and development of test benches to verify comprehensive Design-for-Test (DFT) architecture that supports ATE screening
• Collaborate with the design/design-verification and PD teams to enable the integration and validation of the test logic in all phases of the implementation and post…
• Work with the team on Innovative Hardware DFT & test strategy aspects for new silicon device models, bare die & stacked die

What you need

• 8–14 yrs of experience
• Verilog
• UVM
• Python
• Perl
• Test cases
• VLSI
• B.Tech or B.E.

Good to have

• Routing and switching