ASIC DFT DV Engineer || System Verilog, UVM || JTAG, MBIST || Exp : 8+ years

About the role

You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive high-quality DFT verification. The job requires the candidate to have the ability to craft solutions and debug efficiently.

What you'll do

• Work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive high-quality DFT verification

What you need

• 8–14 yrs of experience
• UVM
• Verilog
• VLSI
• B.Tech or B.E.