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ASIC DFT Engineer || MBIST, SCAN, ATPG, JTAG || Exp 4 to 8 years

Cisco·Bengaluru

Pay not stated4–8 yrsFull-time
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About the role

Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs. The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship.

What you'll do

  • Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs

What you need

  • 4–8 yrs of experience
  • B.Tech or B.E.

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