ASIC DFT Engineer || MBIST, SCAN, ATPG, JTAG || Experience - 4 to 8 years

About the role

Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs. The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship. You are an ASIC Design for Test Hardware Engineer with 4-8 years of related work experience with a broad mix of technologies.

What you'll do

• Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs

What you need

• 4–8 yrs of experience
• VLSI
• Any graduate