ASIC DFT Engineering Technical Leader | ATPG, MBIST, SSN, SCAN | 12+ years

About the role

You will be in the Silicon One development organization as an ASIC Implementation Technical Lead in Bangalore India with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle.

What you'll do

• Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs
• Responsible for development of innovative DFT IP in collaboration with the multi-functional teams
• Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post…
• Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die

What you need

• 12–22 yrs of experience
• Python
• Perl
• Verilog
• VLSI
• Routing and switching
• B.Tech or B.E.