ASIC Digital Design, Sr Manager - 17878

About the role

ASIC Digital Design, Sr Manager - 17878 at Synopsys (incl. Ansys). Lead a team of design and verification engineers in Noida, managing performance, growth, and day-to-day execution across multiple ASIC projects.

What you'll do

• Lead a team of design and verification engineers in Noida, managing performance, growth, and day-to-day execution across multiple ASIC projects
• Own the verification strategy and environment architecture for complex, high-speed protocol designs, defining testplans and coverage models that catch real issues
• Drive technical decisions around verification flows, including SystemVerilog, UVM, behavioral modeling, and coverage-driven verification
• Work directly with architects, RTL designers, and VIP teams to align on design intent, resolve ambiguities, and ensure functional correctness before tapeout
• Identify design gaps and propose corrective actions when documented functionality does not match implementation or customer requirements

What you need

• 15–27 yrs of experience
• Verilog
• UVM
• VLSI
• Python
• Bash
• Perl
• Any graduate