ASIC Digital Design, Sr Staff Engineer - DDR/LPDDR

About the role

ASIC Digital Design, Sr Staff Engineer - DDR/LPDDR at Synopsys (incl. Ansys). Lead a team of verification engineers through full IP verification cycles, from test plan definition through coverage closure and signoff.

What you'll do

• Lead a team of verification engineers through full IP verification cycles, from test plan definition through coverage closure and signoff
• Build and evolve SystemVerilog/UVM verification environments for DesignWare synthesizable IP cores, ensuring they scale across multiple product generations
• Define test plans that cover corner cases, protocol compliance, and system-level interactions, then review and guide implementation across the team
• Write and debug complex testbenches, checkers, and assertions for serial interface protocols and memory controllers, including DDR and LPDDR where applicable
• Extract, analyze, and drive functional coverage and code coverage metrics to closure, identifying gaps and adjusting strategy in real time

What you need

• 6–11 yrs of experience
• Verilog
• UVM
• Test cases
• M.Tech or B.Tech or B.E.