ASIC Digital Design, Sr Staff Engineer

About the role

ASIC Digital Design, Sr Staff Engineer at Synopsys (incl. Ansys). Lead and execute scan insertion and ATPG (Automatic Test Pattern Generation) flows for complex ASIC designs.

What you'll do

• Lead and execute scan insertion and ATPG (Automatic Test Pattern Generation) flows for complex ASIC designs
• Work closely with RTL and Verification teams to ensure DFT requirements are integrated early in the design cycle
• Analyze and resolve DFT-related issues using tools such as Spyglass DFT, ensuring robust test coverage and manufacturability
• Perform scan STA (Static Timing Analysis) to validate timing closure and optimize testability paths
• Collaborate with cross-functional teams to define and implement best practices for DFT methodologies and flows

What you need

• 3–10 yrs of experience
• Python
• Perl
• VLSI
• Any graduate