ASIC Digital Design, Sr Staff Engineer

About the role

ASIC Digital Design, Sr Staff Engineer at Synopsys (incl. Ansys). Own the full lifecycle of complex subsystem design from requirements and architecture through RTL development, verification collaboration, implementation handoff.

What you'll do

• Own the full lifecycle of complex subsystem design from requirements and architecture through RTL development, verification collaboration, implementation handoff
• Craft subsystem architecture and functional specifications, define micro-architecture, and write production-quality RTL using industry best practices
• Drive RTL quality checks including lint, CDC, RDC, and work closely with verification teams to ensure functional correctness and coverage closure
• Integrate and design around standard protocols including PCIe, DDR, UFS, USB, and AMBA-based interconnects
• Implement low power design techniques across clock gating, power gating, and multi-voltage domains, ensuring power intent is captured and verified

What you need

• 8–14 yrs of experience
• Verilog
• VLSI
• B.Tech or B.E. or M.Tech