ASIC Digital Design, Staff Engineer

About the role

ASIC Digital Design, Staff Engineer at Synopsys (incl. Ansys). Own RTL and micro-architecture for one or more PCIe controller subsystems or major features (block through subsystem integration).

What you'll do

• Own RTL and micro-architecture for one or more PCIe controller subsystems or major features (block through subsystem integration)
• Write design specs, implement production RTL, and drive your area through verification, synthesis/timing closure support, and design convergence
• Resolve complex design and debug issues in your domain; escalate architecture trade-offs with clear options
• Participate in and lead design reviews; enforce coding standards, CDC/RDC, and quality for your code
• Collaborate with verification, formal, emulation, and physical design to close bugs and integration issues

What you need

• 8–14 yrs of experience
• VLSI
• Any graduate

Good to have

• Python
• Perl