ASIC Digital Design, Staff Engineer

About the role

ASIC Digital Design, Staff Engineer at Synopsys (incl. Ansys). Own end-to-end verification for MphyV6, UFS, and UniPro IP blocks, from test planning through coverage closure and sign-off.

What you'll do

• Own end-to-end verification for MphyV6, UFS, and UniPro IP blocks, from test planning through coverage closure and sign-off
• Build and extend UVM testbenches in SystemVerilog, including agents, sequences, scoreboards, coverage models, and protocol checkers
• Write constrained-random and directed tests that expose corner cases, protocol violations, and timing edge conditions
• Debug complex failures using Verdi at the waveform, transaction, and protocol level, performing root-cause analysis on RTL and testbench issues
• Translate protocol specifications into executable test plans, SystemVerilog assertions, and functional coverage models

What you need

• UVM
• Verilog
• Test cases
• Root cause analysis
• Any graduate