ASIC Digital Design, Staff Engineer

About the role

ASIC Digital Design, Staff Engineer at Synopsys (incl. Ansys). Build and maintain UVM-based verification environments for DesignWare IP cores across USB, PCI Express, Ethernet, and AMBA protocols.

What you'll do

• Build and maintain UVM-based verification environments for DesignWare IP cores across USB, PCI Express, Ethernet, and AMBA protocols
• Develop test plans by analyzing specifications, identifying coverage holes, and defining verification strategies at both unit and system levels
• Write SystemVerilog testbenches, constrained-random tests, directed tests, and functional coverage models that drive quality metrics to closure
• Debug RTL and testbench issues using VCS, NC, or MTI simulators, trace waveforms, and work with design engineers to resolve root causes
• Manage regressions, analyze coverage reports, close functional and code coverage gaps, and drive IP to signoff quality

What you need

• 5–9 yrs of experience
• Verilog
• UVM
• Python
• Test cases
• Perl
• M.Tech or B.Tech or B.E.