ASIC Digital Design, Staff Engineer

About the role

ASIC Digital Design, Staff Engineer at Synopsys (incl. Ansys). Design and code RTL for high-speed Ethernet IP cores ranging from 100G to 1.6T, focusing on low latency and timing closure in complex datapath and control logic.

What you'll do

• Design and code RTL for high-speed Ethernet IP cores ranging from 100G to 1.6T, focusing on low latency and timing closure in complex datapath and control logic
• Translate protocol specifications and functional requirements into micro-architecture and detailed design documents for DesignWare IP in Ethernet, AMBA AXI, CHI, PCIe
• Build and refine directed Verilog testbenches to improve functional and code coverage, analyzing metrics and defining targeted test cases that catch real bugs
• Perform technical reviews of functional specs, micro-architecture documents, and RTL code from peers across global design teams
• Drive timing analysis and closure for high-speed designs using synthesis, STA, lint, CDC, and formal verification flows

What you need

• 6–11 yrs of experience
• Verilog
• VLSI
• Perl
• Test cases
• B.Tech or B.E.