Senior Engineer IP
Eaton·Pune
- Can I apply
- Open to any education · Senior level
- Pay
- Pay not stated
- Source
- From the company's careers page · today
- How to apply
- On Eaton's site: account needed, ~10–15 min
Early: posted 6 h ago on their own site
ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |8-12 years| Pune)
Cisco·Pune
Pay not stated8–12 yrsFull-time
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About the role
Understand and implement verification scenarios per full chip analog and digital verification test plans Analyse coverage, add scenarios to enhance coverage and debug functional simulations, add corner verification cases and identify and resolve functional bugs FW/C-Coding and verification of CPU sub-systems with FW
What you'll do
- Analyse coverage, add scenarios to enhance coverage and debug functional simulations, add corner verification cases and identify and resolve functional bugs
What you need
- 8–12 yrs of experience
- C
- UVM
- Verilog
- Python
- Test cases
- Any graduate
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