ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |8-12 years| Pune)

About the role

You will work with Cisco's outstanding Silicon Photonics team.

What you'll do

• As a Verification Engineer, you will work with a diverse team of engineers spanning multiple disciplines
• At the concept phase you will create verification documentation and work with senior engineers to help with defining the verification methodology and developing…
• During the initial design phase, you will be a part of block level verification and then you will transition to full chip verification
• Run verification at block & chip level with various high-speed IPs integrated like ODSP, D2D IP, SerDes XSR, SerDes PAM4 integrated drivers/TIA, and control functions
• Develop functional coverage models, assertions, and debug complex verification issues within a UVM-based framework

What you need

• 8–12 yrs of experience
• UVM
• Verilog
• Python
• C
• FPGA
• VLSI
• M.Tech or B.Tech or B.E.

Good to have

• Test cases