ASIC front-end verification engineer

About the role

Designs, analyzes, develops, modifies and evaluates VLSI components and hardware systems. Determines architecture and logic design, design verification through software developed for component and system simulation, and builds physical implementations through development of multidimensional designs involving the layout of complex integrated circuits.

What you'll do

• Be exposed to the latest verification methodologies like UVM and enable complex feature verification suites
• Architect and Develop block level verification environments for sub-system and fullchip using System Verilog and UVM methodology. (30%)
• Define, architect, code, and deliver verification suites/tests for ASICs that enable faster, denser
• Verify large ASIC blocks independently and rapidly and sign off them for tape-out with analysis of code coverage, functional coverage and Gate level simulation. (30%)
• Work closely with logic designers to resolve bugs and software developers to assist in software and bring-up development. (10%)

What you need

• UVM
• Verilog
• Python
• VLSI
• Perl
• Any graduate