ASIC Physical Design, Staff Engineer- 18861

About the role

ASIC Physical Design, Staff Engineer- 18861 at Synopsys (incl. Ansys). Close timing on high performance memory IP including DDR, LPDDR, HBM, and SoC designs across multiple process corners and operating modes.

What you'll do

• Close timing on high performance memory IP including DDR, LPDDR, HBM, and SoC designs across multiple process corners and operating modes
• Own static timing analysis from constraint development through final signoff using PrimeTime, PTECO, and DMSA
• Debug and resolve complex timing violations including asynchronous domain crossings, multi-corner convergence issues, and setup/hold trade-offs
• Implement engineering change orders to fix functional bugs and timing failures without destabilizing already-closed paths
• Build and maintain automation scripts in Python, Perl, Tcl, and shell to streamline STA workflows, report generation, and ECO implementation

What you need

• 5–9 yrs of experience
• VLSI
• Python
• Perl
• M.Tech or B.Tech or B.E.