ASIC RTL Design Engineer (Sr. Engr / Sr. Lead Engr)

About the role

This role offers a position in system power management IP cores and subsystem design, targeted for variety of industry leading Snapdragon SoCs for mobile, compute, IoT and Automotive markets.

What you'll do

• Micro-architecture and RTL design for IP Cores / subsystems
• Work in close coordination with Systems, Verification, SoC, SW, PD & DFT teams for design convergence
• Enable SW teams to use HW blocks
• Qualify designs using static tool checks including Lint, CDC, CLP etc
• Synthesis, LEC and Netlist CLP

What you need

• 3–6 yrs of experience
• Verilog
• IoT
• B.Sc or B.Tech or B.E. or BCA or M.Sc or M.Tech or MCA

Good to have

• Python
• Travel booking
• Perl