ASIC RTL Design Verification Manager

About the role

The role requires deep technical expertise in c/c++/ASM SystemVerilog/UVM-based verification, strong understanding of digital RTL and SoC architectures, and demonstrated experience building and leading high-performing verification teams. He will work closely with RTL design, architecture, and program management teams to deliver high-quality, functionally correct RTL and achieve predictable tape-out schedules.

What you'll do

• RTL Verification Leadership Own end-to-end RTL functional verification for ASIC/SoC programs from specification through RTL sign-off
• Define verification strategy, architecture, methodology, execution plans, and sign-off criteria
• Drive verification planning and execution at full-chip SoC levels
• Establish clear verification milestones aligned with RTL development and tape-out schedules
• Drive verification quality, predictability, efficiency, and reuse across semiconductor programs

What you need

• 17–30 yrs of experience
• Verilog
• C++
• UVM
• C
• B.Sc or M.Sc or B.Tech or B.E.

Good to have

• Python